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Integrated Circuit Systems, Inc.
ICS9248-171
Advance Information
AMD - K7TM System Clock Chip
Recommended Application: ALI 1647 style chipset Output Features: * 1 - Differential pair open drain CPU clocks * 1 - Single-ended open drain CPU clock * 13 - SDRAM @ 3.3V * 7 - PCI @3.3V * 2 - AGP @ 3.3V * 1 - 48MHz, @3.3V * 1 - REF @3.3V, (selectable strength) through I2C Features: * Up to 147MHz frequency support * Support power management: DG stop, PCI stop and Power down Mode from I2C programming. * Spread spectrum for EMI control (0 to -0.5% down spread, 0.25% center spread). * Uses external 14.318MHz crystal Skew Specifications: * CPUT - CPUC: <250ps * PCI - PCI: <500ps * CPU - SDRAM: <350ps * SDRAM - SDRAM: <250ps * AGP - AGP: <250ps * PCI - AGP: <350ps * CPU - PCI: <3ns
Pin Configuration
*DG_STOP# *PD# GND X1 X2 AVDD **FS0/REF0 VDD **FS1/AGP0 AGP1 GND *FS2/PCICLK_F PCICLK0 PCICLK1 PCICLK2 GND VDD *MODE/PCICLK3 PCICLK4 PCICLK5 AVDD48 **FS3/48MHz GND SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CPUCLKT0 CPUCLKC0 CPUCLKT1 SDATA SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDD GND SDRAM6 SDRAM7 SDRAM8 SDRAM9 GND VDD SDRAM10(PCI_STOP#)* SDRAM11 SDRAM12
48-Pin 300mil SSOP & 240mil TSSOP package
Notes: REF0 could be 1X or 2X strength controlled by I2C. * Internal Pull-up Resistor of 120K to VDD ** Internal pull-down of 120K to GND.
Block Diagram
PLL2 48MHz
Functionality
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU SDRAM 66.66 66.66 66.66 100.00 100.00 66.66 100.00 100.00 100.00 133.33 120.00 120.00 133.33 100.00 133.33 133.33 90.00 90.00 101.00 101.00 100.00 66.66 100.00 100.00 100.00 133.33 126.00 126.00 133.33 100.00 133.33 133.33
X1 X2
XTAL OSC PLL1 Spread Spectrum
REF0
CPU DIVDER
2
CPUCLKT (1:0) CPUCLKC0
SDATA SCLK FS (3:0) PD# PCI_STOP# DG_STOP# MODE
Control Logic
SDRAM DIVDER
Stop
13
SDRAM (12:0)
PCI DIVDER
Stop
6
PCICLK (5:0) PCICLK_F
Config. Reg.
AGP DIVDER Stop
2
AGP (1:0)
Power Groups
AVDD = Xtal, Core PLL AVDD48 = 48MHz, Fixed PLL
9248-171 Rev - 12/29/00 Third party brands and names are the property of their respective owners.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.
ICS9248-171
ICS9248-171
Advance Information
Pin Descriptions
PIN NUMBER 1 PIN NAME DG_STOP# 1 TYPE IN DESCRIPTION DG_STOP halts SDRAM and/or AGP clocks at logic "0" when driven low. The stops selection can be programed through I2C. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Crystal input,nominally 14.318M Hz. Crystal output, nominally 14.318MHz. Ground pins Power supply pins, nominal 3.3V Analog power supply pin, nominal 3.3V Frequency select pin. 14.318 M Hz reference clock. Frequency select pin. AGP outputs defined as 2X PCI. These may not be stopped. AGP outputs defined as 2X PCI. These may not be stopped. Free running PCICLK not stoped by PCI_STOP# Frequency select pin. PCI clock outputs. PCI clock output. Function select pin, 1=Desktop M ode, 0=M obile M ode. Analog power supply pin, nominal 3.3V Frequency select pin. 48MHz output clock Clock input of I2C input, 5V tolerant input Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low SDRAM clock output. SDRAM clock outputs. Data pin for I2C circuitry 5V tolerant "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. "Complementory" clocks of differential pair CPU outputs. This open drain output need an external 1.5V pull-up.
2 4 5 3, 11, 16, 23, 29, 34, 41, 48 8, 17, 28, 35, 40 6 7 9 10 12 20, 19, 15, 14, 13 18 21 22 24 27 25, 26, 30, 31, 32, 33, 36, 37, 38, 39, 42, 43 44 45, 47 46
PD# 1 X1 X2 GND VDD AVDD FS0 2, 3 REF0 FS1 2, 3 AGP0 AGP1 PCICLK_F FS2 1, 3 PCICLK (5:4) (2:0) PCICLK3 M ODE1, 3 AVDD48 FS3 2, 3 48MHz SCLK PCI_STOP# 1 SDRAM 10 SDRAM (12:11, 9:0 ) SDATA CPUCLKT (1:0) CPUCLKC0
IN IN OUT PWR PWR PWR IN OUT IN OUT OUT OUT IN OUT OUT IN PWR IN OUT IN IN OUT OUT I/O OUT OUT
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Internal pull-down resistor of 120K to GND. 3: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9248-171
Advance Information
General Description
The ICS9248-171 is a main clock synthesizer chip for AMD-K7 based systems with ALI 1647 style chipset. This provides all clocks required for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-171 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
MODE, Pin 18 (Latched Input) 0 1 Pin 27 PCI_STOP# (Input) SDRAM10 (Output)
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ICS9248-171
Advance Information
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description FS3 FS2 FS1 FS0 CPUCLK SDRAM PCICLK (MHz) (MHz) (MHz) Bit2 Bit7 Bit6 Bit5 Bit4 0 0 0 0 0 66.66 66.66 33.33 0 0 0 0 1 66.66 100.00 33.33 0 0 0 1 0 100.00 66.66 33.33 0 0 0 1 1 100.00 100.00 33.33 0 0 1 0 0 100.00 133.33 33.33 0 0 1 0 1 120.00 120.00 30.00 0 0 1 1 0 133.33 100.00 33.33 0 0 1 1 1 133.33 133.33 33.33 0 1 0 0 0 90.00 90.00 30.00 0 1 0 0 1 101.00 101.00 33.67 0 1 0 1 0 100.00 66.66 33.33 0 1 0 1 1 100.00 100.00 33.33 0 1 1 0 0 100.00 133.33 33.33 0 0 1 0 1 126.00 126.00 31.50 0 1 1 1 0 133.33 100.00 33.33 0 1 1 1 1 133.33 133.33 33.33 1 0 0 0 0 102.00 102.00 34.00 1 0 0 0 1 102.00 136.00 34.00 1 0 0 1 0 136.00 102.00 34.00 1 0 0 1 1 136.00 136.00 34.00 1 0 1 0 0 103.00 103.00 34.33 1 0 1 0 1 103.00 137.33 34.33 1 0 1 1 0 137.33 103.00 34.33 1 0 1 1 1 137.33 137.33 34.33 1 1 0 0 0 105.00 105.00 35.00 1 1 0 0 1 105.00 140.00 35.00 1 1 0 1 0 140.00 140.00 35.00 1 1 0 1 1 107.00 107.00 35.66 1 1 1 0 0 107.00 142.66 35.66 1 1 1 0 1 142.66 142.66 35.66 1 1 1 1 0 110.00 110.00 36.66 1 1 1 1 1 146.66 146.66 36.66 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit 2, 7:4 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs AGP (MHz) 66.66 66.66 66.66 66.66 66.66 60.00 66.66 66.66 60.00 67.33 66.66 66.66 66.66 63.00 66.66 66.66 67.99 67.99 67.99 67.99 68.66 68.66 68.66 68.66 69.99 69.99 69.99 71.33 71.33 71.33 73.33 73.33 Spread Precentage +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread
PWD
Bit 2, Bit 7:4
00000 Note1
Bit 3 Bit 1 Bit 0
0 0 0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. The I2C readback of the power up default indicates the revision ID in bits 2, 7:4 as shown.
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ICS9248-171
Advance Information
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 20 19 18 15 14 13 12 PWD X 1 1 1 1 1 1 1 DESCRIPTION MODE# PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 PCICLK_F
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
10 9 22 43 7 47, 46 45
PWD
X 1 1 1 1 1 1 1 FS3# AGP1 AGP0
DESCRIPTION
48MHz SDRAM0
REF0 - 1X or 2X d e fa u l t = 1 = 1 X
CPUCLKT0, CPUCLKC0 CPUCLKT1
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 31 30 27 26 25 PWD X X X 1 1 1 1 1 FS0# FS1# FS2# SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 DESCRIPTION
Byte 4: Reserved , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 PIN# PWD 0 DESCRIPTION Bit (7:6) = 01 DG_STOP# will stop SDRAM & AGP clocks Bit (7:6) = 10 DG_STOP# will stop SDRAM clocks only Bit (7:6) = 11 DG_STOP# will stop AGP clocks only SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
39 38 37 36 33 32
1 1 1 1 1 1 1
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
42 1 1 1 1 1 1 1 1
DESCRIPTION
Reserved Reserved Reserved Reserved Reserved Reserved Reserved SDRAM1
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 1 1 1
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
Notes:
Note: Don't write into this register, writing into this register can cause malfunction
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
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ICS9248-171
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD VIN = 0 V; Inputs with no pull-up resistors Input Low Current IIL1 VIN = 0 V; Inputs with pull-up resistors Input Low Current IIL2 Operating IDD3.3OP66 CL = 0 pF; Select @ 66MHz Supply Current IDD3.3OP100 CL = 0 pF; Select @ 100MHz IDD3.3OP133 CL = 0 pF; Select @ 133MHz Power Down Input frequency Input Capacitance1 Clk Stabilization1 Skew1 PD Fi CIN CINX TSTAB VDD = 3.3 V; Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq. MIN 2 VSS-0.3 -5 -200 TYP MAX UNITS VDD+0.3 V 0.8 V 5 A A A 180 600 16 5 45 3 350 3 mA A MHz pF pF ms ps ns
12 27
14.318
tCPU-SDRAM VT = 50% tCPU-PCI 1 Guaranteed by design, not 100% tested in production.
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ICS9248-171
Advance Information
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output Low Current Rise Time
1
SYMBOL ZO VOH2B VOL2B IOL2B tr2B tf2B VDIF VDIF VX dt2B tsk2B tjcyc-cyc2B tjabs2B
CONDITIONS VO = VX Termination to Vpull-up(external) Termination to Vpull-up(external) VOL = 0.3 V VOL = 0.3 V, VOH = 1.2 V VOH = 1.2 V, VOL = 0.3 V Note 2 Note 2 Note 3 VT = 50% VT = 50% VT = VX VT = 50%
MIN
TYP
MAX
UNITS
1 1.2 0.4 18 0.9 0.9 0.4 0.2 550 45 Vpullup(external) + 0.6 Vpullup(external) + 0.6 1100 55 250 250 +250 V V mA ns ns V V mV % ps ps ps
Fall Time1 Differential voltage-AC1 Differential voltage-DC1 Differential Crossover Voltage1 Duty Cycle1 Skew1 Jitter, Cycle-to-cycle1 Jitter, Absolute1
-250
Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input level and VCP is the "complement" input level. 3 - Vpullup(external) = 1.5V, Min = Vpullup (external)/2-150mV; Max=(Vpullup (external)/2)+150mV
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ICS9248-171
Advance Information
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew
1 1 1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 Tsk
1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5V VT = 1.5V
MIN 2.6
TYP
19
MAX UNITS V 0.4 V -16 mA mA 2 2 ns ns % ps
Duty Cycle
45
55 500
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_F
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 Tsk
1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 50% VT = 50%
MIN 2.6
TYP
12
MAX UNITS V 0.4 V -12 mA mA 2 2 ns ns % ps
Duty Cycle
1
45
55 500
Skew (window)
Guaranteed by design, not 100% tested in production.
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ICS9248-171
Advance Information
Electrical Characteristics - 48MHz, REF0
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tj1s5 tjabs5
CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
16
MAX UNITS V 0.4 V -22 mA mA 2 2 ns ns % ns ns
Duty Cycle
45 -1
55 0.5 1
Jitter, One Sigma Jitter, Absolute
1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM (12:0)
TA = 0 - 70 C; VDD = 3.3 V +/-5%, C L = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle
1 1 1
SYMBOL VOH3 VOL3 IOH3 IOL3 Tr3 Dt3
1
CONDITIONS IOH = -11 mA IOL = 11 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 50%
MIN 2
TYP
12
MAX UNITS V 0.4 V -12 mA mA 2.2 2.2 ns ns % ps
Tf3 1
1 1
45
55 250
Tsk VT = 50% Guarenteed by design, not 100% tested in production.
Skew (window)
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ICS9248-171
Advance Information
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controlle r (Host) Start Bit Address D2(H ) Dummy Command Code A CK Dummy Byte Count A CK Byte 0 A CK Byte 1 A CK Byte 2 A CK Byte 3 A CK Byte 4 A CK Byte 5 A CK Byte 6 A CK Byte 7 A CK Stop Bit ICS (Sla ve/Re ceiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controlle r (Host) Start Bit Address D3(H ) ICS (Slave/Rece ive r)
A CK
ACK
A CK Byte Count Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9248-171
Advance Information
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248171 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS9248-171
Advance Information
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-171. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-171 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-171 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248-171. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
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ICS9248-171
Advance Information
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT CPUCLKC
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-171 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS9248-171
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SY MBOL
In Millimeters COMMON DIMENSIONS MIN MA X 2.413 0.203 0.203 2.794 0.406 0.343
In Inches COMMON DIMENSIONS MIN MA X .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N V A RIA TIONS N 28 34 48 56 64
0.127 0.254 SEE V A RIA TIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE V A RIA TIONS .395 .291 .015 .420 .299 .025
0.635 BA SIC 0.508 1.016 SEE V A RIA TIONS 0 8
0.025 BA SIC .020 .040 SEE V A RIA TIONS 0 8
D mm. MIN 9.398 11.303 15.748 18.288 20.828 MA X 9.652 11.557 16.002 18.542 21.082 MIN .370 .445 .620 .720 .820
D (inch) MA X .380 .455 .630 .730 .830
6/1 /0 0 R EVB
J E D E C M O-1 1 8 D OC # 1 0- 00 34
Ordering Information
ICS9248yF-171-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.
ICS9248-171
Advance Information
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 0.05 0.80 0.17 1.20 0.15 1.05 0.27 .002 .032 .007 .047 .006 .041 .011
A A1 A2 b c D E E1 e L N aaa VARIATIONS N
0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20
.0035 .008 SEE VARIATIONS 0.319 .236 .244 0.020 BASIC .018 .30 SEE VARIATIONS 0 8 .004
0.50 BASIC 0.45 0.75 SEE VARIATIONS 0 8 0.10
D mm. MIN 7.70 9.60 10.90 10.90 12.40 13.90 16.90 MAX 7.90 9.80 11.10 11.10 12.60 14.10 17.10 MIN .303 .378 .429 .429 .488 .547 .665
D (inch) MAX .311 .386 .437 .437 .496 .555 .673
7/6/00 Rev B
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil)
28 36 40 44 48 56 64
MO-153 JEDEC Doc.# 10-0039
Ordering Information
ICS9248yG-171-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
15
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.

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